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bn:00066732n
Noun Concept
Categories: All Wikipedia articles written in American English, All articles containing potentially dated statements, All articles needing additional references, Articles with short description, Instruction set architectures
EN
reduced instruction set computing  reduced instruction set computer  RISC  reduced instruction set  Reduced Instruction Set Code
EN
(computer science) a kind of computer architecture that has a relatively small set of computer instructions that it can perform WordNet 3.0
Definitions
Relations
Sources
EN
(computer science) a kind of computer architecture that has a relatively small set of computer instructions that it can perform WordNet 3.0 & Open English WordNet
In computer science, a reduced instruction set computer is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Wikipedia
A CPU design philosophy favoring an instruction set reduced in size and complexity of addressing, to simplify implementation, instruction level parallelism, and compiling Wikipedia Disambiguation
Processor executing one instruction in minimal clock cycles Wikidata
IS A
computer architecture
design paradigm
processor design
instruction set
HAS KIND
Berkeley RISC
HAS INSTANCE
MMIX
ANTONYM
complex instruction set computing
CATEGORY DOMAIN
computer science
DERIVATIVE WORK
ARM architecture
DIFFERENT FROM
RNA-induced silencing complex
OPPOSITE OF
complex instruction set computing
WordNet 3.0 & Open English WordNet
EN
reduced instruction set computing, reduced instruction set computer, RISC
Wikipedia
EN
reduced instruction set computer
Wikidata
EN
reduced instruction set computing
Wikipedia Redirections
EN
reduced instruction set, Reduced Instruction Set Code, Reduced instruction set computer, reduced instruction set computing, RISC, RISC-based, RISC-based computer design approach, RISC-based system, RISC architecture, RISC architectures, RISC instruction set, RISC principles, RISC processor, RISC System/6000 SP
Wikidata Alias
EN
RISC

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