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bn:01643409n
Noun Concept
Categories: Encapsulados, Zócalos de CPU
ES
pin grid array  PPGA
ES
La matriz de rejilla de pines[1]​[2]​ o PGA es una interfaz de conexión a nivel físico para microprocesadores y circuitos integrados o microchips. Wikipedia
Definitions
Relations
Sources
ES
La matriz de rejilla de pines[1]​[2]​ o PGA es una interfaz de conexión a nivel físico para microprocesadores y circuitos integrados o microchips. Wikipedia
IS A
EN
semiconductor package
HAS KIND
Socket 754
Socket FS1
PAC611
Socket 563
Socket AM3
+3 relations
HAS INSTANCE
PGA132
Wikipedia
ES
pin grid array
Wikidata
ES
Pin grid array
Wikipedia Redirections
ES
PPGA
Wikidata Alias
ES
PPGA

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